This invention relates generally to a current interface circuit and, more specifically, to a current interface circuit which is particularly well-suited for use as an input stage to a high speed comparator.
Very high speed comparators are essential to the realization of devices such as fast and accurate successive approximation A to D converters. One approach to a 12-bit A to D converter utilizes a fast voltage comparator, an SAR (successive approximation register), and a high speed D to A converter. A conventional 12-bit converter of this type is shown in FIG. 1 of the article entitled "A Fast Latching Current Comparator for 12-Bit A/D Applications" by Paul A. Crolla, IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 6., Dec. 1982. This figure is reproduced as FIG. 1 in this disclosure.
Presently available voltage comparators have a response time on the order of 48 nanoseconds for 0.5 LSB overdrive. However, the speed of the overall SAR loop is hampered by the capacitance (C.sub.x in FIG. 1) present at the comparator input. In a typical 12-bit system which employs a conventional voltage comparator, the total stray capacitance (typically 30 picofarads) together with the 2500 ohm conversion resistor sets up a time constant which can introduce unwanted time delays into the loop. In order to reduce this delay, Schottky diodes are often placed across the input terminals to clamp or limit the voltage excursion at the input nodes.
An alternative approach involves the use of a current, rather than voltage, comparator as the polarity discriminator. A converter utilizing this approach is shown in FIG. 2 of the above-mentioned article and is reproduced as FIG. 2 of this Specification. The input terminal of a current comparator is sensitive to signal current rather than voltage changes and, accordingly, has a low input impedance. Due to the low input impedance, voltage excursions at the input node are minimal and the impact of the delay attributable to the capacitance at the input node may be reduced by an order of magnitude. Furthermore, a current detecting polarity discriminator is a logical interface to a current output DAC converter and the need for Schottky diode clamps at the input node may be eliminated.
Accordingly, an object of the present invention is to provide a current interface circuit which may be used as the input stage in a current comparator to discriminate the polarity of input signal current while maintaining a low impedance at the input node.
Another object of the present invention is to provide an input circuit for use in a comparator which eliminates the need for clamp circuitry at the input node.
Yet another object of the present invention is to provide a circuit for use as the input stage of a comparator to virtually eliminate attenuation of the input signal due to the use of external application resistors to provide for preferential offsets (e.g., the bipolar mode in an A to D converter application).
These and other objects are attained in accordance with the present invention by a current interface circuit which includes an impedance buffering circuit which maintains a very low impedance at an input node, and which has first and second current outputs. The impedance buffering circuit produces an increase in current flow at the first current output and a decrease in current flow at the second current output in response to a change in magnitude of the input current flow. Circuitry connected to the current outputs of the buffer compensates for errors which would otherwise be introduced by the buffer circuitry and reflects the input current changes to a circuit output which is connected to a load.
A preferred embodiment of the current interface circuit of the present invention comprises an operational amplifier, a pair of current mirrors, and circuitry for connecting the current mirrors to an output node. The operational amplifier receives a signal from an input current source and has a feedback connection from its output to the input. The amplifier also has a pair of three terminal, complementary output transistors which are connected at their emitters to the amplifier output. The collectors of each transistor are connected to the controlled leg of respective current mirrors. The controllable leg of each current mirror is connected to an output node of the interface circuit. In an especially preferred embodiment, each controlled leg is connected to the output terminal by means of complementary three terminal transistors having the same geometry as the amplifier output transistors. When a bipolar pair is used, the controllable legs of the respective current mirrors are connected to the emitters of the respective devices, the collectors are connected to each other and to the output node, and the base of each of the transistors is connected to a biasing voltage. These complimentary devices provide compensation for errors caused by base current variations in the complementary bipolar transistor pair used as the output devices in the operational amplifier.
Another preferred embodiment of the current interface circuit of the present invention comprises an operational amplifier having first and second current outputs, and circuitry for connecting these outputs to respective first and second nodes of a differential voltage output. The first current output is connected directly to the first output node, which is also connected by a resistance network to a voltage supply. The second current output is connected to the controlled leg of a current mirror. The controllable leg of the current mirror is connected to the second node of the differential voltage output. This second node of the voltage output is also preferably connected to a voltage source by a resistance network. In an especially preferred embodiment, the controllable leg of the current mirror is connected to the second output node by the main current conducting path of a compensating transistor. The control terminal of the compensating transistor is connected to the control terminal of one of a pair of complementary output devices of the operational amplifier. A second compensating transistor has a main current conducting path connected in series with a current source, and has a control terminal connected to the second current output. The current source is set to supply a current which is equal in magnitude to the quiescent current flowing through the complementary output pair of the operational amplifier. The currents flowing in the control legs of these compensating transitors provide compensation for errors caused by base current variations in the complementary output devices of the operational amplifier.
In the preferred embodiments just described, the impedance at the input node is kept low by the feedback connection from the amplifier output to the negative input. The output devices of the amplifier are both on and conducting the same emitter current under quiescent conditions. When a change in input current occurs, the emitter current through one of the output devices is reduced by an amount which is equal to one-half the magnitude of the change, while the emitter current of the other output device is increased by a like amount. These changes are reflected in the controllable leg of the current mirror or mirrors, which are connected to the output nodes. Respective errors due to the base currents of the amplifier output devices are compensated. The original change in the input current is thus effectively reconstructed at the output node.